Google's AI chips finally run on Meta's preferred software

For years, the path to running large AI models on Google’s custom hardware has been blocked by a software wall. Meta, the company behind the dominant PyTorch framework, did not want to rewrite its code to run on Google’s chips. That tension has broken. Google’s Tensor Processing Units, or TPUs, now power production AI workloads at Meta. This marks a major step in making Google’s silicon a serious competitor to Nvidia’s GPUs in the data centers of major tech firms.

The breakthrough comes from a new version of the SGLang inference engine. This tool allows AI models to run on TPUs using PyTorch, the standard language for machine learning development. Previously, developers had to use Google’s own JAX framework to access these chips. The new setup removes that barrier. It allows Meta to deploy its existing workloads on Google hardware without a massive rewrite. A matching open-source version for vLLM, another popular inference engine, was also released today.

Zongwei Zhou, the PyTorch-TPU lead at Meta, confirmed the deployment. He stated that the new SGLang-TorchTPU setup is running in production at Meta today. Zhou described the result as a remarkably mature, PyTorch-native serving stack. This work came from a close three-way collaboration between Meta, Google, and the SGLang team. Zhou’s team operates at RadixArk, a startup founded by the creators of the SGLang engine.

Jana van Greunen, director of PyTorch engineering at Meta, emphasized the strategic importance of this move. She noted that Meta cannot be constrained by a single hardware architecture. According to Van Greunen, this new tool enables the company to deploy its PyTorch workloads to Google TPUs. Google stated that it co-developed this TorchTPU system directly with Meta’s PyTorch team to ensure compatibility.

This is not the first time Meta has looked at Google’s chips. Google calls the older PyTorch/XLA bridge a predecessor to the new system. Reports from last year indicated that Meta research teams used TPUs through that older bridge between 2020 and 2023. However, Meta canceled those contracts at the time. The current push was aimed specifically at Meta because the company refused to migrate its core infrastructure to JAX. Now, with a native PyTorch option, that objection is gone.

The physical location of these chips remains somewhat unclear. However, talks last year reportedly involved Google Cloud TPU rentals for 2026, with potential purchases planned for 2027. Meta later signed a multi-year rental agreement, according to previous reports. This suggests a long-term commitment to diversifying its hardware portfolio beyond Nvidia.

The timing of this announcement is significant. It came one day after Amazon announced it was open-sourcing TorchNeuron. That is Amazon’s own native PyTorch backend for its Trainium2 and Trainium3 chips. Both Google and Amazon appear to be making moves to loosen Nvidia’s software lock-in. By providing native PyTorch support, they are making it easier for developers to choose alternatives without changing their coding workflows.

Performance metrics suggest the new setup is competitive. A tuned vLLM setup serving the Kimi K3 model reportedly tops 700 tokens per second for a single user on the seventh-generation Ironwood TPU. This speed figure comes from Inferact, a startup founded by vLLM’s creators. Its test used 16 Ironwood chips with speculative decoding. That setup outperformed vLLM’s published setup on 16 Nvidia GB200s, which reached 452 tokens per second. For smaller batch sizes without speculative decoding, the new kernels deliver roughly 1.4 to 2 times the throughput of the GB200 baseline.

The team plans to keep adding support for more models. SGLang-TorchTPU will start with DeepSeek V4.1 Flash and Reflection Beam. RadixArk is also working toward Day 0 TPU support for new open models. This means support will be available on release day by the first quarter of 2027. Google, Meta, and RadixArk plan to share more details at the SGLang Summit 2026, which is scheduled for November 12-13 in San Francisco.